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fractional - n frequency synthesizer data sheet adf4153 rev. f document feed back information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2003 C 2013 analog devices, inc. all rights reserved. technical support www.analog.com features rf bandwidth to 4 ghz 2.7 v to 3.3 v power supply separate v p allows extended tuning voltage y v ersion available : ?40c to +125c programmable fractional modulus programmable charge pump currents 3 - wire serial interface analog and digital lock de tect power - down mode pin - compatible with adf4110 / adf4111 / adf4112 / adf4 113 and adf4106 consistent rf output phase loop filter design possible with adis impll qualified for automotive applications applications catv equipment base stations for mobile radio (gsm, pcs, dcs, wimax, su percell 3g, cdma, w - c dma) wireless handsets (gsm, pcs, dcs, cdma, w - cdma) wireless lans, pmr communications test equipment general description the adf4153 is a fractional - n frequency synthesizer that implements local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. it consists of a low noise digital phase frequency detector (pfd), a precision charge pump, and a programmable reference divider. there is a - based fractional interpolator to allow programmable fractional - n division. the int, frac, and mod registers define an overall n divider ( n = ( int + ( frac / mod ))) . in addition, the 4 - bit reference counter (r counter) allows selectable refin frequencie s at the pfd input. a complete phase - locked loop (pll) can be implemented if the synthesizer is used with an external loop filter and a voltage controlled oscillator (vco). a simple 3 - wire interface controls all on - chip registers. the device operates wi th a power supply ranging from 2.7 v to 3.3 v and can be powered down when not in use. functional block dia gram lock detect n-counter c p rfcp3 rfcp2 rfcp1 reference d at a le 24-bit d at a register clk ref in a v dd agnd v dd v dd dgnd r div n div dgnd cpgnd dv dd v p sdv dd r set rf in a rf in b output mux ? + high-z phase frequenc y detec t or adf4153 third order fractiona l interpol a t or modulus reg fraction reg integer reg current setting 2 doubler 4-bit r counter charge pum p 03685-001 muxout figure 1.
adf4153 data sheet rev. f | page 2 of 24 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 3 specifications ..................................................................................... 4 timing specifications .................................................................. 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configurations and function descript ions ........................... 7 typical performance characteristics ............................................. 8 circuit description ........................................................................... 9 reference input section ............................................................... 9 rf input stage ............................................................................... 9 rf int divider ............................................................................. 9 i nt, frac, mod, and r relationship ..................................... 9 rf r counter ................................................................................ 9 phase frequency detector (pfd) and charge pump ............ 1 0 muxout and lock detect ...................................................... 10 input shift registers ................................................................... 10 program modes .......................................................................... 10 n divider register, r0 ............................................................... 16 r divider register, r1 ................................................................ 16 control register, r2 ................................................................... 16 noise and spur register, r3 ...................................................... 17 reserved bits ............................................................................... 17 initialization sequence .............................................................. 18 rf synthesizer: a worked example ........................................ 18 modulus ....................................................................................... 18 reference doubler and reference divider ............................. 18 12- bit programmable modulus ................................................ 18 fastlock with spurious optimization ...................................... 19 spur mechanisms ....................................................................... 19 spur consistency ........................................................................ 20 phase resync ............................................................................... 20 filter design adisimpll ....................................................... 20 interfacing ................................................................................... 20 pcb design guidelines for chip scale package .................... 21 applications information .............................................................. 22 local oscillator for a gsm base station transmitter ........... 22 outline dimensions ....................................................................... 23 ordering guide .......................................................................... 24 automotive products ................................................................. 24
data sheet adf4153 rev. f | page 3 of 24 revision history 11/1 3 re v. e to rev. f change to i cp sink/source parameter, table 1 .............................. 4 changes to ordering guide ........................................................... 24 7/12 rev. d to rev. e updated outline dimensions ........................................................ 23 changes to ordering guide ........................................................... 24 8 /10 rev. c to rev. d changes to features section ............................................................ 1 changes to noise characteristics parameter, table 1 .................. 5 changes to figure 4 ........................................................................... 7 changes to ordering guide ........................................................... 2 4 added automotive products section ........................................... 24 10/0 8 rev. b to rev. c added y version (throughout) ...................................................... 1 changes to ordering guide ........................................................... 23 08/05 rev. a to rev. b changes to features .......................................................................... 1 changes to applica tions ................................................................... 1 changes to specifications ................................................................. 3 changes to absolute maximum ratings ........................................ 5 changes to figure 7 to figure 9 ....................................................... 7 deleted figure 8 to figure 10; renumbered sequentially ........... 8 deleted figure 11 and figure 14; renumbered sequentially ...... 9 changes to table 9 .......................................................................... 13 added init ialization sequence section ........................................ 17 changes to fastlock with spurious optimization section ........ 18 inserted figure 16; renumbered sequentially ............................ 18 added spur mechanisms section ................................................. 18 added table 11; renumbered sequentially ................................. 18 added spur consistency section .................................................. 19 changes to phase resync section ................................................. 19 inserted figure 17; renumbered sequentially ............................ 19 deleted spurious signals predicting where they will appear section .............................. 20 changes to figure 19 ...................................................................... 20 changes to figure 20 ...................................................................... 21 added applications section .......................................................... 21 changes to figure 22 caption ....................................................... 22 cha nges to ordering guide ........................................................... 22 1/04 rev. 0 to rev. a renumbered figures and tables ...................................... universal changes to specifications ................................................................. 3 changes to pin function description ............................................ 7 changes to rf power - down section ........................................... 17 changes to pcb design guidelines for chip scale package section ............................................................................... 2 1 updated outline dimensions ........................................................ 22 updated ordering guide ............................................................... 22 7/03 revision 0: initial version
adf4153 data sheet rev. f | page 4 of 24 specifications av dd = dv dd = sdv dd = 2.7 v to 3.3 v; v p = av dd to 5.5 v; agnd = dgnd = 0 v; t a = t min to t max , unless otherwise noted; dbm referred to 50 ?. table 1 . parameter b version 1 y version 2 unit test conditions/comments rf characteristics (3 v) see figure 12 for input circuit rf input frequency (rf in ) 0.5/4.0 0.5/4.0 ghz min/max b version: ? 8 dbm minimum /0 dbm max imum 0.5/4.0 0.5/4.0 ghz min/max y version: ? 6.5 dbm minimum /0 dbm maximum for lower frequencies, ensure slew rate (sr) > 400 v/s 1.0/4.0 1.0/4.0 ghz min/max ? 10 dbm/0 dbm min imum /max im um reference characteristics see figure 11 for input circuit ref in input frequency 10/250 10/250 mhz min/max for f < 10 mhz, use a dc - coupled , cmos - compatible square wave; slew rate > 25 v/s ref in input sensitivity 0.7/ av d d 0.7/ av dd v p - p min/max biased at av dd /2 3 ref in input capacitance 10 10 pf max ref in input current 100 100 a max phase detector phase detector frequency 4 32 32 mhz max charge pump i cp sink/source programmable; see table 9 high value 5 5 ma typ with r set = 5.1 k low value 312.5 312.5 a typ absolute accuracy 2.5 2.5 % typ with r set = 5.1 k r set range 1.5/10 1.5/10 k min/max i cp three - state leakage current 1 4.5 na typ sink and source current matchi ng 2 2 % typ 0.5 v < v cp < v p C 0.5 i cp vs. v cp 2 2 % typ 0.5 v < v cp < v p C 0.5 i cp vs. temperature 2 2 % typ v cp = v p /2 logic inputs v inh , input high voltage 1.4 1.4 v min v inl , input low voltage 0.6 0.6 v max i inh /i inl , input current 1 1 a max c in , input capacitance 10 10 pf max logic outputs v oh , output high voltage 1.4 1.4 v min open - drain 1 k pull - up to 1.8 v v ol , output low voltage 0.4 0.4 v max i ol = 500 a power supplies av dd 2.7/3.3 2.7/3.3 v min/v max dv dd , sdv dd av dd av dd v p av dd /5.5 av dd /5.5 v min/v max i dd 24 24 ma max 20 ma typical low power sleep mode 1 1 a typ
data sheet adf4153 rev. f | page 5 of 24 parameter b version 1 y version 2 unit test conditions/comments noise characteristics normalized phase noise floor (pn synth ) 5 ? 220 ? 220 dbc/hz typ pll loop bw = 500 khz normalized 1/f noise (pn 1_f ) 6 ?114 ?114 dbc/hz typ measured at 10 khz offset, normalized to 1 ghz phase noise p erformance 7 @ vco output 1750 mhz output 8 ? 102 ? 102 dbc/hz typ @ 5 khz offset, 25 mhz pfd frequency 1 operating temperature for b version is ?40c to +85c. 2 operating temperature for y version is ?40c to + 125 c. 3 ac coupling ensures av dd /2 bias. 4 guaranteed by design. sample tested to ensure compliance. 5 the synthesizer phase noise floor is estimated by measuring the in - band phase noise at the output of the vco and subtracting 20 log ( n ) (where n is the n divider value) and 10 log( f pfd ) . pn synth = pn tot ? 10 log( f pfd ) ? 20 log( n ) . 6 the pll phase noise is composed of 1/f ( flicker) noise plus the normalized pll noise floor. the formula for calculating the 1/f noise contribution at an rf frequency , f rf , and at a n offset frequency , f , is given by pn = p 1_f + 10 log(10 khz/f) + 20 log(f rf /1 ghz). both the normalized phase noise floor and flicker noise are modeled in adisimpll. 7 the phase noise is measured with the ev - adf4153 sd1z and the agilent e5500 phase noise system. 8 f refin = 100 mhz; f pfd = 25 mhz; offset frequency = 5 khz; rf out = 1750 mhz; n = 70; loop bw = 20 khz; lo w est noise mode. timing specification s av dd = dv dd = sdv dd = 2.7 v to 3.3 v; v p = av dd to 5.5 v; agnd = dgnd = 0 v; t a = t min to t max , unless otherwise noted; dbm re ferred to 50 ?. table 2 . parameter limit at t min to t max (b version) unit test conditions/comments t 1 20 ns min le setup time t 2 10 ns min data to clk setup time t 3 10 ns min data to cl k hold time t 4 25 ns min cl k high duration t 5 25 ns min clk low duration t 6 10 ns min clk to le setup time t 7 20 ns min le pulse width clk d at a le le db23 (msb) db22 db2 db1 (contro l bit c2) db0 (lsb) (contro l bit c1) t 1 t 2 t 3 t 7 t 6 t 4 t 5 03685-026 figure 2 . timing diagram
adf4153 data sheet rev. f | page 6 of 24 absolute maximum rat ings t a = 25c, gnd = agnd = dgnd = 0 v, v dd = av dd = dv dd = sdv dd , unless otherwis e noted. table 3 . parameter rating v dd to gnd ? 0.3 v to +4 v v dd to v dd ? 0.3 v to +0.3 v v p to gnd ? 0.3 v to +5.8 v v p to v dd ? 0.3 v to +5.8 v digital i/o voltage to gnd ? 0.3 v to v dd + 0.3 v analog i/o voltage to gnd ? 0.3 v to v dd + 0.3 v ref in , rf in to gnd ? 0.3 v to v dd + 0.3 v operating temp erature range industrial (b version) ? 40c to +85c extended (y version) ? 40c to +125c storage temperature range ? 65c to +125c maximum junction temperature 150c tssop ja thermal impedance 112c/w lfcsp ja thermal impedance (paddle soldered) 30.4c/w reflow soldering peak temperature 260c time at peak temperature 40 sec maximum junction temperature 150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. t his device is a high performance rf integrated circuit with an esd rating of <2 kv, and it is esd sensitive. proper precautions should be taken for handling and assembly. esd caution
data sheet adf4153 rev. f | page 7 of 24 pin configuration s and function descrip tions 03685-002 1 2 3 4 5 6 7 8 16 15 14 13 12 1 1 10 9 cp cpgnd agnd a v dd rf in a rf in b r set dv dd muxout le sdv dd ref in dgnd clk dat a v p adf4153 t op view (not to scale) figure 3 . tssop pin configuration 03685-003 pin 1 indic a t or 1 cpgnd 2 agnd 3 agnd 4 rf in b 5 rf in a 13 dat a 14 le 15 muxout notes 1. the lfcs p has an exposed p addle th a t must be connected t o gnd. 12 clk 1 1 sdv dd 6 a v dd 7 a v dd 8 ref in 10 dgnd 9 dgnd 18 v p 19 r set 20 cp 17 dv dd 16 dv dd t op view (not to scale) adf4153 figure 4 . lfcsp pin configuration table 4 . pin function descriptions pin no. tssop pin no. lfcsp mnemonic description 1 19 r set connecting a resistor betwe en r set and ground sets the maximum charge pump output current. the relationship between i cp and r set is set cpmax r i 5 . 25 = where r set = 5.1 k and i cp max = 5 ma. 2 20 cp charge pump output. when enabled, cp provides i cp to the external loop filter , which in turn drives the external vco. 3 1 cpgnd charge pump ground. this is the ground return path for the charge pump. 4 2, 3 agnd analog ground. this is the ground return path of the prescaler. 5 4 rf in b complementary input to the rf prescaler. th is pin should be decoupled to the ground plane with a small bypass capacitor, typically 100 pf (see figure 12). 6 5 rf in a input to the rf prescaler. this small signal input is normally ac - coupled from the vco. 7 6, 7 av dd posit ive power supply for the rf section. decoupling capacitors to the digital ground plane should be placed as close as possible to this pin. av dd has a value of 3 v 10%. av dd must have the same voltage as dv dd . 8 8 ref in reference input. this is a cmos i nput with a nominal threshold of v dd /2 and an equivalent input resistance of 100 k (see figure 11 ). this input can be driven from a ttl or cmos crystal oscillator, or it can be ac - coupled. 9 9, 10 dgnd digital ground. 10 11 sdv dd - power. decoupling capacitors to the digital ground plane should be placed as close as possible to this pin. sdv dd has a value of 3 v 10%. sdv dd must have the same voltage as dv dd . 11 12 clk serial clock input. the serial clock is used to clock in the serial data to the registers. the data is latched into the shift r egister on the clk rising edge. this input is a high impedance cmos input. 12 13 data serial data input. the serial data is loaded msb first; the two lsbs are the control bits. this input is a high impedance cmos input. 13 14 le load enable, cmos input. when le is high, the data stored in the shift registers is loaded into one of four latches; the latch is selected using the control bits. 14 15 muxout this multiplexer output allows either the rf lock detect, the scaled rf, or the scaled reference freq uency to be externally accessed. 15 16, 17 dv dd positive power supply for the digital section. decoupling capacitors to the digital ground plane should be placed as close as possible to this pin. dv dd has a value of 3 v 10%. dv dd must have the same vo ltage as av dd . 16 18 v p charge pump power supply. this should be greater than or equal to v dd . in systems where v dd is 3 v, it can be set to 5.5 v and used to drive a vco with a tuning range of up to 5.5 v. 21 ep exposed pad. the exposed paddle must be connected to gnd.
adf4153 data sheet rev. f | page 8 of 24 typical performance characteristics loop bandw idth = 20 khz, reference = 250 mhz, vco = sirenza 1750t vco , evaluation board = ev - adf4153 sd1z , measurements taken on the agilent e5500 phase noise system. phase noise (dbc/hz) ?30 ?60 ?80 ?140 ?130 ?120 ? 1 10 ?150 ?160 ?170 ?90 ?100 ?70 ?50 ?40 20khz loo p b w , lowest noise mode rf = 1.7202mhz, pfd = 25mhz, n = 68, frac = 101, mod = 125, i cp = 625a, dsb integr a ted phase error = 0.23 rms sirenz a 1750t vco 1k 10k 1m 10m 100m 100k 03685-004 frequenc y (hz) figure 5 . single - sideband phase noise plot (lowest noise mode) phase noise (dbc/hz) ?30 ?60 ?80 ?140 ?130 ?120 ? 1 10 ?150 ?160 ?170 ?90 ?100 ?70 ?50 ?40 1k 10k 1m 10m 100m 100k 03685-005 frequenc y (hz) 20khz loo p b w , low noise and spur mode rf = 1.7202mhz, pfd = 25mhz, n = 68, frac = 101, mod = 125, i cp = 625a, dsb integr a ted phase error = 0.33 rms sirenz a 1750t vco figure 6 . single - sideband phase noise plot (low noise and spur mode) phase noise (dbc/hz) ?30 ?60 ?80 ?140 ?130 ?120 ? 1 10 ?150 ?160 ?170 ?90 ?100 ?70 ?50 ?40 1k 10k 1m 10m 100m 100k 03685-006 frequenc y (hz) 20khz loo p b w , low spur mode rf = 1.7202mhz, pfd = 25mhz, n = 68, frac = 101, mod = 125, i cp = 625a, dsb integr a ted phase error = 0.36 rms sirenz a 1750t vco figure 7 . single - sideband phase noise plot (low spur mode) frequenc y (ghz) amplitude (dbm) 5 0 ?5 ?10 ?20 ?15 ?25 ?30 ?35 0 0.5 1.0 1.5 4.0 3.5 3.0 2.5 2.0 4.5 p = 4/5 p = 8/9 03685-0 1 1 figu re 8 . rf input sensitivity v c p (v) 6 0 ?6 i c p (ma) 4 2 ?2 ?4 ?5 ?3 ?1 1 3 5 0 1 2 3 4 5 03685-012 figure 9 . charge pump output characteristics temper a ture (c) ?90 ?94 ?104 ?60 100 ?40 phase noise (dbc/hz) ?20 0 20 40 60 ?96 ?98 ?92 ?102 ?100 80 03685-014 figure 10 . phase noise vs. temperature
data sheet adf4153 rev. f | page 9 of 24 circuit description reference input section the reference input stage is shown in figure 11 . sw1 and sw2 are normally closed switches. sw3 is normally open. when power - down is initiated, sw3 is closed and sw1 and sw2 are opened. this ensures that there is no loading of the ref in pin on power - down. 03685-027 buffer t o r counter ref in 100k ? nc sw2 sw3 no nc sw1 power-down contro l figure 11 . reference input stage rf input stage the rf input stage is shown in figure 12 . it is followed by a 2 - stage limiting amplifier to generate the current - mode logic (cml) clock levels needed for the prescaler. bias gener a t or 1.6v agnd a v dd 2k? 2k? rf in b rf in a 03685-015 figure 12 . rf input stage rf int divider the rf int cmos counter allows a division ratio in the pll feedback counter. division ratios from 31 to 511 are allowed. int, frac, mod, and r relationship the int, frac, and mod values, in conjunction with the r counter, make it possible to generate output frequencies that are spaced by fractions of the phase frequency detector (pfd). see the rf synthesizer: a worked example section fo r more information. the rf vco frequency (rf out ) equation is rf out = f pfd ( int + ( frac / mod )) (1) w here : rf out is the output frequency of the external voltage controlled oscillator (vco). int is the preset divide ratio of the binary 9 - bit counter (31 to 511). mod is the preset fractional modulus (2 to 4095). frac is the numerator of the fractional division (0 to mod ? 1). the pfd frequency is given by: f pfd = r e f in (1 + d )/ r (2) where: ref in is the reference input frequency. d is the ref in doubler bit. r is the pr eset divide ratio of the binary 4 - bit programmable re ference counter (1 to 15). rf r counter the 4 - bit rf r counter allows the input reference frequency (ref in ) to be divided down to produce the reference clock to the pfd. division ratios from 1 to 15 are allowed. third-order fractiona l interpol a t or frac v alue mod reg int reg rf n divider n = int + frac/mod from rf input s t age t o pfd n-counter 03685-016 figure 13 . rf n d ivider
adf4153 data sheet rev. f | page 10 of 24 phase frequency dete ctor (pfd) and charge pump the pfd takes inputs from the r counter and n counter and produces an output proportional to the phase and frequency difference between them. figure 14 is a simplified schemat ic of the phase frequency detector. the pfd includes a fixed delay element that sets the width of the antibacklash pulse, which is typically 3 ns. this pulse ensures that there is no dead zone in the pfd transfer function and gives a consistent reference s pur level. u3 clr2 q2 d2 u2 down u p hi hi c p ?in +in charge pum p del a y clr1 q1 d1 u1 03685-017 figure 14 . pfd simplified schematic muxout and lock dete ct the output multiplexer on the adf4153 allows the user to acce ss various internal points on the chip. the state of mux out is controlled by m3, m2, and m1 (see table 8 ). figure 15 shows the muxout section in block diagram form. digi t a l lock detect r counter divider logic low dgnd contro l mux muxout dv dd three-s ta te output n counter divider analog lock detect logic high 03685-018 s figure 15 . muxout schematic input shift register s the adf4153 digital section includes a 4 - bit rf r counter, a 9 - bit rf n counter, a 12 - bit frac counter, and a 12 - bit modulus counter. data is clocked into the 24 - bit shift register on each rising edge of clk. the data is clocked in msb first. data is transferred from the shift register to one of four latches on the rising edge of le. the destination latch is determined by the state of the two control bits (c2 and c1) in the shift register. these are the 2 lsbs, db1 and db0, as shown in figure 2 . the truth table for these bits is shown in table 5 . table 6 shows a summary of how the registers are programmed. program modes table 5 through table 10 show how to set up the program modes in t he adf4153. the adf4153 programmable modulus is double buffered. this means that two events have to occur before the part uses a new modulus value. first, the new modulus value is latched into the device by writing to the r divider register. second, a new write must be performed on the n divider register. therefore , to ensur e that the modulus value is loaded correctly, the n divider register must be written to any time that the modulus value is updated. table 5 . c2 and c1 truth tabl e control bits c2 c1 register 0 0 n divider register 0 1 r divider register 1 0 control register 1 1 noise and spur register
data sheet adf4153 rev. f | page 11 of 24 table 6 . register summary noise and spur reg (r3) db10 db9 db8 db7 db6 db5 db4 db3 db1 db0 c2 (1) c1 (1) t1 0 0 0 t5 t6 t7 t8 noise and spur mode db2 0 noise and spur mode rese r ved n divider reg (r0) db20 db19 db18 db17 db16 db15 db14 db13 db12 db 1 1 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (0) f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f 1 1 f12 n1 n3 n4 n5 n6 contro l bits contro l bits contro l bits contro l bits 12-bit fractiona l v alue (frac) db23 db22 db21 n7 n8 n9 9-bit integer v alue (int) n2 f astlock fl1 r divider reg (r1) db18 db17 db16 db15 db14 db13 db12 db 1 1 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (1) m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m 1 1 m12 r1 r3 r4 12-bit interpol a t or modulus v alue (mod) 4-bit r counter r2 muxout 0 db20 db19 p1 m1 db23 db22 db21 m2 m3 p3 load contro l rese r ved rese r ved prescaler contro l reg (r2) reference doubler db14 db13 db12 db 1 1 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (0) u1 u2 u3 u4 u5 cp0 cp1 cp2 u6 s1 s2 s3 s4 c p current setting pd polarit y resync ld p power- down c p three-s ta te counter reset db15 cp3 cp/2 03685-019
adf4153 data sheet rev. f | page 12 of 24 table 7 . n divider register map (r0) f12 f1 1 f10 f3 f2 f1 fractiona l v alue (frac) 0 .......... 0 0 .......... 0 0 .......... 0 0 .......... 0 . .......... . . .......... . . .......... . 1 .......... 1 4092 1 .......... 1 4093 1 .......... 1 4094 1 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 1 1 1 0 0 1 1 . . . 0 0 1 1 0 1 0 1 . . . 0 1 2 3 . . . 0 1 0 1 .......... 1 4095 n9 n8 n7 n6 n5 n4 n3 n2 n1 integer v alue (int) 0 0 0 1 1 31 0 0 1 0 0 32 0 0 1 0 1 33 0 0 1 0 0 34 . . . . . . . . . . . . . . . . . . 1 1 1 1 1 509 1 1 1 1 0 510 1 0 0 0 0 . . . 1 1 1 1 1 1 0 0 0 . . . 1 1 1 1 0 0 0 . . ... 1 1 1 1 1 0 0 1 . . . 0 1 1 1 51 1 fl1 f astlock 0 norma l oper a tion 1 f astlock enabled db20 db19 db18 db17 db16 db15 db14 db13 db12 db 1 1 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (0) f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f1 1 f12 n1 n3 n4 n5 n6 contro l bits 12-bit fractiona l v alue (frac) db23 db22 db21 n7 n8 n9 9-bit integer v alue (int) n2 f astlock fl1 03685-020
data sheet adf4153 rev. f | page 13 of 24 table 8 . r divider register map (r1) m12 interpol a t or modulus v alue (mod) m 1 1 m10 m3 m2 m1 0 0 .......... 0 1 0 2 0 0 .......... 0 1 1 3 0 0 .......... 1 0 0 4 . . .......... . . . . . . .......... . . . . . . .......... . . . . 1 1 .......... 1 0 0 4092 1 1 .......... 1 0 1 4093 1 1 .......... 1 1 0 4094 1 0 0 0 . . . 1 1 1 1 1 .......... 1 1 1 4095 rf r counter divide r a tio r4 r3 r2 r1 0 0 0 0 . . . 1 12 1 13 1 14 1 0 0 0 1 . . . 1 1 1 1 0 1 1 0 . . . 0 0 1 1 1 0 1 0 . . . 1 2 3 4 . . . 0 1 0 1 15 p1 prescaler 0 4/5 1 8/9 db18 db17 db16 db15 db14 db13 db12 db 1 1 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (1) m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m 1 1 m12 r1 r3 r4 contro l bits 12-bit interpol a t or modulus v alue (mod) 4-bit r counter r2 muxout 0 db20 db19 p1 m1 db23 db22 db21 m2 m3 p3 load contro l rese r ved prescaler p3 load contro l 0 norma l oper a tion 1 load resync m3 m2 m1 muxout 0 three-s ta te output digi t a l lock detect analog lock detect 0 0 n divider output logic high logic low 0 1 r divider output 1 1 f astlock switch 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 03685-021
adf4153 data sheet rev. f | page 14 of 24 table 9 . control register map (r2) u3 power-down 0 norma l oper a tion 1 power-down u4 ld p 0 1 24 pfd cycles 40 pfd cycles i c p (ma) cp3 cp2 cp1 cp0 2.7k? 5.1k? 10k? 0 1.18 0.63 0.32 0 2.46 1.25 0.64 0 3.54 1.88 0.96 0 4.72 2.50 1.28 0 5.9 3.13 1.59 0 7.08 3.75 1.92 0 8.26 4.38 2.23 0 9.45 5.00 2.55 1 0.59 0.31 0.16 1 1.23 0.63 0.32 1 1.77 0.94 0.48 1 2.36 1.25 0.64 1 2.95 1.57 0.8 1 3.54 1.88 0.96 1 4.13 2.19 1.12 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 4.73 2.50 1.28 u5 pd polarit y 0 neg a tive 1 positive u2 c p three-s ta te 0 disabled 1 three-s ta te u1 counter reset 0 disabled enabled 1 reference doubler u6 0 disabled 1 enabled reference doubler db14 db13 db12 db 1 1 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (0) u1 u2 u3 u4 u5 cp0 cp1 cp2 u6 s1 s2 s3 s4 contro l bits c p current setting pd polarit y resync ld p power- down c p three-s ta te counter reset db15 cp3 cp/2 s4 s3 s2 s1 resync 0 1 1 0 0 2 0 1 3 . . . . . . . . . 1 1 13 1 0 14 1 0 0 0 . . . 1 1 1 0 1 1 . . . 0 1 1 1 15 03685-022
data sheet adf4153 rev. f | page 15 of 24 table 10 . noise and spur register (r3) low spur mode 00000 low noise and spur mode 11 100 lowest noise mode 1111 1 db10 db9 db8 db7 db6 db5 db4 db3 db1 db0 c2 (1) c1 (1) t1 0 0 0 t5 t6 t7 t8 contro l bits noise and spur mode db2 0 noise and spur mode rese r ved rese r ved rese r ved db10, db5, db4, db3 noise and spur setting db9, db8, db7, db6, db2 rese r ved 0 these bits must be set t o 0 for norma l oper a tion. 03685-023
adf4153 data sheet rev. f | page 16 of 24 n divider register, r0 with r0[1, 0] set to [0, 0], the on - chip n div ider register is programmed. table 7 shows the input data format for programming this register. 9 - bit int value these nine bits control what is loaded as the int value. this is used to determine the overall feedback division fact or. it is used in equation 1 (see the int, frac, mod, and r relationship section). 12- bit frac value these 12 bits control what is loaded as the frac value into the fractional interpolator. this is part of what determines the ove rall feedback division factor. it is also used in equation 1. the frac value must be less than or equal to the value loaded into the mod register. fastlock when set to logic high, fastlock is enabled. this sets the charge pump current to its maximum value. when set to logic low, the charge pump current is equal to the value programmed into the function register. also, if muxout is programmed to setting the fastlock switch, muxout is shorted to ground when the fastlock bit is 1 and is high impedance when thi s bit is 0. r divider register, r1 with r1[1, 0] set to [0, 1], the on - chip r divider register is programmed. table 8 shows the input data format for programming this register. load control when set to logic high, the value being programmed in the modulus is not loaded into the modulus. instead, it sets the resync delay of the - . this is done to ensure phase resync when changing frequencies. see the phase resync section for more information and a worked example. muxo ut the on - chip multiplexer is controlled by db 2 2, db 21, and db 20 on the adf4153. see table 8 for the truth table. digital lock detect the digital lock detect output goes high if there are 24 succes - sive pfd cycles with an input er ror of less than 15 ns (for ldp is 0, see the control register, r2 section for a more thorough explanation of the ldp bit). it stays high until a new channel is programmed or until the error at the pfd input exceeds 30 ns for one or more cycles. if the loop bandwidth is narrow compared to the pfd frequency, the error at the pfd inputs may drop below 15 ns for 24 cycles around a cycle slip. therefore, the digital lock detect may go falsely high for a short period until the error ag ain exceeds 30 ns. in this case, the digital lock detect is reliable only as a loss - of - lock detector. prescaler (p/p + 1) the dual - modulus prescaler (p/p + 1), along with the int, frac, and mod counters, determines the overall division ratio from the rf in to the pfd input. operating at cml levels, it takes the clock from the rf input stage and divides it down for the counters. it is based on a synchronous 4/5 core. when set to 4/5, the maximum rf frequency allowed is 2 ghz. therefore, when operating the ad f4153 above 2 ghz, this must be set to 8/9. the prescaler limits the int value. with p = 4/5, n min = 31. with p = 8/9, n min = 91. 4 - bit r counter the 4 - bit r counter allows the input reference frequency (ref in ) to be divided down to produce the reference clock to the phase frequency detector (pfd). division ratios from 1 to 15 are allowed. 12- bit interpolator mod value these programmable bits set the fractional modulus. this is the ratio of the pfd frequency to the channel step resolution on the rf output. refer to the rf synthesizer: a worked example section for more information. the adf4153 programmable modulus is double buffered. this means that two events have to occur before the part uses a new modulus value. first, the new m odulus value is latched into the device by writing to the r divider register. second, a new write must be performed on the n divider register. therefore, any time that the modulus value has been updated, the n divider register must then be written to in or der to ensure that the modulus value is loaded correctly. control register, r2 with r2[1, 0] set to [1, 0], the on - chip control register is programmed. table 9 shows the input data format for programming this register. rf counter reset db2 is the rf counter reset bit for the adf4153. when this is 1, the rf synthesizer counters are held in reset. for normal operation, this bit should be 0. rf charge pump three - state db3 puts the charge pump into three - state mode when programmed to 1. it should be set to 0 for normal operation. rf power - down db4 on the adf4153 provides the programmable power - down mode. setting this bit to 1 performs a power - down. setting this bit to 0 returns the synthesizer to normal operation. while in software po wer - down mode, the part retains all information in its registers. only when supplies are removed are the register contents lost.
data sheet adf4153 rev. f | page 17 of 24 when a power - down is activated, the following events occur: 1. all active dc current paths are removed. 2. the synthesizer counters are forced to their load state conditions. 3. the charge pump is forced into three - state mode. 4. the digital lock detect circuitry is reset. 5. the rf in input is debiased. 6. the input register remains active and capable of loading and latching data. lock detect prec ision (ldp) when db5 is programmed to 0, 24 consecutive pfd cycles of 15 ns must occur before digital lock detect is set. when this bit is programmed to 1, 40 consecutive reference cycles of 15 ns must occur before digital lock detect is set. phase detecto r polarity db6 in the adf4153 sets the phase detector polarity. when the vco characteristics are positive, this should be set to 1. when they are negative, it should be set to 0. charge pump current setting db7, db8, db9, and db10 set the charge pump curre nt setting. this should be set to the charge pump current that the loop filter is designed with (see table 9 ). ref in doubler setting db11 to 0 feeds the ref in signal directly to the 4 - bit rf r counter, disabling the doubler. setti ng this bit to 1 multiplies the ref in frequency by a factor of 2 before feeding into the 4 - bit r counter. when the doubler is disabled, the ref in falling edge is the active edge at the pfd input to the fractional synthesizer. when the doubler is enabled, b oth the rising and falling edges of ref in become active edges at the pfd input. w hen the doubler is enabled and the lowest spur mode is chos en, the in - band phase noise performance is sensitive to the ref in duty cycle. the phase noise degradation can be as much as 5 db for the ref in duty cycles outside a 45% to 55% range. the phase noise is insensitive to the ref in duty cycle in the lowest noise mode and in the lowest noise and spur mode. the phase noise is insensitive to ref in duty cycle when the doubler i s disabled. the maximum allowed ref in frequency when the doubler is enabled is 30 mhz. noise and spur regis ter, r3 with r3[1, 0] set to [1, 1], the on - chip noise and spur register is programmed. table 10 shows the input data for mat for programming this register. noise and spur mode noise and spur mode allows the user to optimize a design either for improved spurious performance or for improved phase noise performance. when the low spur setting is chosen, dither is enabled. this r andomizes the fractional quantization noise so that it resembles white noise rather than spurious noise. as a result, the part is optimized for improved spurious performance. this operation would normally be used when the pll closed - loop bandwidth is wide, for fast - locking applica - tions. (wide - loop bandwidth is seen as a loop bandwidth greater than 1/10 of the rf out channel step resolution (f res ) . ) a wide - loop filter does not attenuate the spurs to the same level as a narrow - loop bandwidth. when the low no ise and spur setting is enabled, dither is disabled. this optimizes the synthesizer to operate with improved noise performance. however, the spurious performance is degraded in this mode compared to the low spur setting. to further improve noise performan ce, the lowest noise setting option can be used, which reduces the phase noise. as well as disabling the dither, it also ensures that the charge pump is operating in an optimum region for noise performance. this setting is extremely useful where a narrow - l oop filter band - width is available. the synthesizer ensures extremely low noise and the filter attenuates the spurs. the typical performance characteristics give the user an idea of the trade - off in a typical w - cdma setup for the different noise and spur s ettings. reserved bits these bits should be set to 0 for normal operation.
adf4153 data sheet rev. f | page 18 of 24 initialization seque nce the following initialization sequence should be followed upon powering up the part: 1. write all zeros to the noise and spur register. this ensures that all te st modes are cleared. 2. write again to the noise and spur register, this time selecting which noise and spur mode is required. for example, writing hex adecimal 0003c7 to the part selects low est noise mode . 3. enable the counter reset in the control register by writing a 1 to db2; also select the required settings in the control register. if using the phase resync function, set the resync bits to the required settings. 4. load the r divider register (with load c ontrol db23 set to 0). 5. load the n divider register. 6. di sable the counter reset by writing a 0 to db2 in the control register. the part now locks to the set frequency. if using the phase resync function, an extra step is needed after step 3. this involves loading the r divider register with load control = 1 and the required delay interval in place of the mod value. the previous sequence can then be f ollowed ensuring that in step 4 the value of mod is written to the r divider register with load control = 0. see the spur consistency and phase resync sections for more information on the phase resync feature. rf synthesizer: a wo rked example the following equation governs how the synthesi zer is programmed: rf out = [ int + ( frac / mod )] [ f pfd ] (3) where: rf out is t he rf frequency output. int is the integer division factor. frac is the fractionality. mod is the modulus. the pfd frequency is given by: f p fd = [ ref in (1 + d )/ r ] (4) where: ref in is the reference frequency input. d is the rf ref in doubler bit. r is the rf reference division factor. for example, in a gsm 1 800 system, where 1.8 ghz rf frequency output (rf out ) is required, a 13 mhz reference frequency input (ref in ) is available and a 200 khz channel resolution (f res ) is required on the rf output. mod = ref in / f res mod = 13 mhz / 200 khz = 65 from equation 4: f pf d = [13 mhz (1 + 0)/1] = 13 mhz (5) 1.8 g = 13 mhz ( int + frac /65) where int = 138; frac = 30 (6) modulus the choice of modulus (mod) depends on the reference signal (ref in ) available and the chann el resolution (f res ) required at the rf output. for example, a gsm system with 13 mhz ref in set s the modulus to 65. this means that the rf output resolution (f res ) is the 200 khz (13 mhz/65) necessary for gsm. with dither off, the fractional spur interval depends on the modulus values chosen. see table 11 for more information. reference doubler an d reference divider the reference doubler on - chip allows the input reference signal to be doubled. this is useful for increasing the pfd comparison frequency. making the pfd frequency higher improves the noise performance of the system. doubling the pfd frequency usually improves noise performance by 3 db. it is important to note that the pfd cannot be operated above 32 mhz due to a limita tion in the speed of the - circuit of the n divider. 12- bit programmable mod ulus unlike most other fractional - n plls, the adf4153 allows the user to program the modulus over a 12 - bit range. this means that the user can set up the part in many different c onfigu - rations for the application, when combined with the reference doubler and the 4 - bit r counter. the following is an example of an application that requires 1.75 ghz rf and 200 khz channel step resolution. the system has a 13 mhz reference signal. o ne possible setup is feeding the 13 mhz directly to the pfd and programming the modulus to divide by 65. this result s in the required 200 khz resolution. another possible setup is using the reference doubler to create 26 mhz from the 13 mhz input signal. t his 26 mhz is then fed into the pfd. the modulus is now programmed to divide by 130. this also results in 200 khz resolution and offers superior phase noise performance over the previous setup.
data sheet adf4153 rev. f | page 19 of 24 the programmable modulus is also very useful for multi - standa rd applications. if a dual - mode phone requires pdc and gsm 1800 standards , the programmable modulus is of great benefit. pdc requires 25 khz channel step resolution, whereas gsm 1800 requires 200 khz channel step resolution. a 13 mhz reference signal ca n be fed directly to the pfd. the modulus is program med to 520 when in pdc mode (13 mhz/520 = 25 khz). the modulus is reprogrammed to 65 for gsm 1800 operation (13 mhz/65 = 200 khz). it is important that the pfd frequency remains constant (13 mhz). this al lows the user to design one loop filter that can be used in both setups without running into stability issues. it is the ratio of the rf frequency to the pfd frequency that affects the loop design. by keeping this relationship constant, the same loop filte r can be used in both applications. fastlock with spurio us optimization as mentioned in the noise and spur mode section, the part can be optimized for spuriou s performance. however, in fast locking applications, the loop bandwidth needs to be wide, and therefore the filter does not provide much attenuation of the spurs. the programmable charge pump can be used to get around this issue. the filter is designed for a narrow - loop bandwidth so that steady - state spurious specifications a re met. this is designed using the lowest charge pump current setting. to implement fastlock during a frequency jump, the charge pump current is set to the maximum setting for the duration of the jump by asserting the fastlock bit in the n divider register . this widens the loop bandwidth, which improves lock time. to maintain loop stability while in wide bandwidth mode, the loop filter needs to be modified. this is achieved by switching in a resistor (r1a) in parallel with the damping resistor in the loop f ilter (see figure 16 ). muxout needs to b e set to the fastlock switch to use the internal switch. for example, if the charge pump current is increased by 16, the damping resistor , r1 , needs to be decreased by ? while in wide bandw idth mode. adf4153 vco c2 c1 cp fl muxout r1 r1 a 03685-029 figure 16 . adf4153 with fastlock the value of r1a is then chosen so that the total parallel resistance of r1 and r1a equals 1/4 of r1 alone. this gives an overall 4 increase in loop bandwidth, while maintaining stab ility in wide bandwidth mode. when the pll has locked to the new frequency, the charge pump is again programmed to the lowest charge pump current setting by setting the fastlock bit to 0. the internal switch opens and the damping resistor reverts to its o riginal value. this narrows the loop bandwidth to its original cutoff frequency to allow better attenuation of the spurs than the wide - loop bandwidth. spur mechanisms the follo wing section describes the three different spur mechan - isms that arise with a f ractional - n synthesizer and how to minimize them in the adf4153. fractional spurs the fractional interpolator in the adf4153 is a third - order - modulator (sd m) with a modulus ( mod ) that is programmable to any integer value from 2 to 4 095. in low spur mod e (dither enabled), the minimum allowed value of mod is 50. the sdm is clocked at the pfd reference ra te ( f pfd ) that allows pll output frequencies to be synthesized at a channel step resolution of f pfd /mod. in lowest noise mode and low noise and spur mode (dither off), the quantization noise from the - modulator appears as frac - tional spurs. the interval between spurs is f pfd /l, where l is the repeat length of the code sequence in the digit al - modulator. for the third - order modulator used in the adf415 3, the repeat length depends on the value of mod, as shown in table 11. table 11 . fractional spurs with dither off condition (dither off) repeat length spur interval if mod is divisible by 2, but not 3 2 mod channel step/2 if mod is divisible by 3, but not 2 3 mod channel step/3 if mod is divisible by 6 6 mod channel step/6 otherwise mod channel step in low spur mode (dither enabled), the repeat length is extended to 2 21 cycles, regardless of t he value of mod, which makes the quantization error spectrum look like broadband noise. this can degrade the in - band phase noise at the pll output by as much as 10 db. therefore, for lowest noise, dither off is a better choice, particularly when the final loop bw is low enough to attenuate even the lowest frequency fractional spur. integer boundary spurs another mechanism for fractional spur creation is interactions between the rf vco frequency and the reference frequency. when these frequencies are not in teger related (which is the p oint of a fractional - n synthesizer), spur sidebands appear on the v co output spectrum at an offset frequency that corre sponds to the beat note or difference frequency between an integer multiple of the reference and the vco fre quency. these spurs are attenuated by the loop filter and are more noticeable on channels close to integer multiples of the reference where the difference frequency can be inside the loop bandwidth, therefore, the name integer boundary spurs.
adf4153 data sheet rev. f | page 20 of 24 reference s purs reference spurs are generally not a problem in fractional - n synthesizers because the reference offset is far outside the loop bandwidth. however, any reference feedthrough mechan - ism that bypasses the loop can cause a problem. one such mechan ism is feedthrough of low levels of on - chip reference switching noise out through the rf in pin back to the vco, resulting in reference spur levels as high as C 90 dbc. care should be taken in the pcb layout to ensure that the vco is well separated from the input reference to avoid a possible feed - through path on the board. spur consistency when jumping from frequency a to frequency b and then back again using some fractional - n synthesizers, the spur levels often differ each time frequency a is programmed. however, in the adf4153, the spur levels on any particular channel are always consistent. phase resync the output of a fractional - n pll can settle to any one of mod phase offsets with respect to the input referenc e, where mod is the fractional modulus. the phas e resync feature in the adf4153 can be used to produce a consistent output phase offset with respect to the input reference. this is necessary in applications where the output phase and frequency are important, such as digital beam - forming. when phase res ync is enabled, an internal timer generates sync signals at intervals of t sync given by the following formula: t sync = resync resync_delay t pfd where t pfd is the pfd reference period. resync is the decimal value programmed in bits db[15 12] of register r2 and can be any integer in the range of 1 to 15. if resync is programmed to its default value of all zeros, then the phase resync feature is disabled. if phase resync is enabled, then resync_delay must be programmed to a value that is an integer mul tip le of the value of mod. resync_delay is the decimal value programmed into the mod bits ( db[133] of register r1 whe n load control (bit db23 of register r1) = 1. when a new frequency is programmed, the second next sync puls e after the le rising edge is use d to resynchronize the out put phase to the reference. the t sync time should be programmed to a value that is a t least as long as the wors t - case lock time. doing so guarantees that the phase resync occurs after the last cycle slip in the pll settling transi ent. in the example shown in figure 17 , the pfd reference is 25 mhz and mod = 125 for a 200 khz channel spacing. t sync is set to 400 s by programming resync = 10 and resync_delay = 1000. le phase frequenc y sync (internal) ?100 0 100 200 1000 300 400 500 600 700 800 900 03685-030 time (s) pl l settles t o correct phase after resync last cycle sli p pl l settles t o incorrect phase t sync figure 17 . phase resync example filter design adi sim pll a filter design and analysis program is available to help the user implement pll design. visit www.analog.com/pll for a free download of the adisimpll software. the soft ware designs, simulates, and analyzes the entire pll frequency domain and time domain response. various passive and active filter architectures are allowed. interfacing the adf4153 has a simple spi? - compatible serial interface for writing to the device. clk, data, and le control the data transfer. when latch enable (le) is high, the 22 bits that are clocked into the input register on each rising edge of sclk are transferred to the appropriate latch. see figure 2 for the timing di agram and table 5 f or the register truth table . the maximum allowable serial clock rate is 20 mhz. aduc812 interface figure 18 shows the interface between the adf4153 and the aduc812 microconverter?. because the aduc812 is based on an 8051 core, this i nterface can be used with any 8 051 - based micro - controller. the mi croconverter is set up for spi master mode with cpha = 0. to initiate the operation, the i/o port driving le is brought low. each latch of the adf4153 needs a 24 - bit word, which is accomplished by writing three 8 - bit bytes from the microconverter to the de vice. after the third byte is written, the le input should be brought high to complete the transfer. aduc812 adf4153 sclock clk d at a le muxout (lock detect) mosi i/o ports 03685-024 figure 18 . aduc812 to adf4153 interface
data sheet adf4153 rev. f | page 21 of 24 when operating in this mode, the maximum sclock rate of the aduc812 is 4 mhz. this means that the maximum rate at which the output frequency can be changed is 180 khz. adsp - 21xx interface figure 19 shows the interface between the adf4153 and the adsp - 21xx digital signal processor. as discussed previously, the adf4153 needs a 24 - bit serial word for each latch write. the easiest way to accomplish this using the adsp - 21xx family is to use the autobuffered transmit mode of operation with alternate framing. this provides a me ans for transmitting an entire block of serial data before an interrupt is generated. set up the word length for eight bits and use three memory locations for each 24 - bit word. to program each 24 - bit latch, store the three 8 - bit bytes, enable the autobuff ered mode, and write to the transmit register of the dsp. this last operation initiates the autobuffer transfer. adsp-21xx adf4153 sclk clk d at a le muxout (lock detect) dt tfs i/o flags 03685-025 figure 19 . adsp - 21xx to adf4153 interface pcb design guideline s for chip scale package the lands on the chip scale p ackage (cp - 20) are rectangular. the pr inted circuit board (p cb) pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. the land should be centered on the pad. this ensures that the solder joint siz e is maximized. the bottom of the chip scale package has a central thermal pad. the thermal pad on the pcb should be at least as large as this exposed pad. on the pcb, there should be a clearance of at least 0.25 mm between the thermal pad and the inner e dges of the pad pattern. this ensures that shorting is avoided. thermal vias can be used on the pcb thermal pad to improve thermal performance of the package. if vias are used, they should be incorporated in the thermal pad at 1.2 mm pitch grid. the via di ameter should be between 0.3 mm and 0.33 mm, and the vi a barrel should be plated with one ounce of copper to plug the via. the user should connect the pdb thermal pad to agnd.
adf4153 data sheet rev. f | page 22 of 24 applications information local oscillator for a gsm base station transmitter figure 20 shows the adf4153 being used with a vco to produce the local oscillator (lo) for a gsm base station transmitter. the reference input signal is applied to the circuit at ref in and, in this case, is terminated in 50 ?. a 25 mhz reference is used, which is fed directly to the pfd. to achieve 200 khz channel spacing, a modulus of 125 is necessary. note that with a modulus of 125, which is not divisible by 2, 3 or 6, subfractional spurs are avoided. see the spur mechanisms section for more information. the charge pump output of the adf4153 drives the loop filter. the charge pump current is i cp = 5 ma. adi s impll is used to calculate the loop filter. it is designed for a loop bandwidth of 20 khz and a phase margin of 45 degrees. the loop filter output drives the vco, which in turn is fed back to th e rf input of the pll synthesizer. it also drives the rf outp ut terminal. a t - circuit configuration p rovides 50 ? matching between the vco output, the rf output, and the rf in terminal of the synthesizer. in a pll system, it is important to know when the loop is in lock. this is achieved by using the muxout signal from the synthesizer. the muxout pin can be programmed to monitor various internal signals in the synthesizer. one of these is the lock detect signal. v dd v p a v dd dv dd adf4153 v p 22nf 82? 160? 270nf vco190-902t v cc rf out 18? 18? 18? 100pf 100pf 1000pf 1000pf 51? 5.1k? ref in sv dd 5 3 4 9 7 15 16 6 14 14 10 2 2 r set muxout lock detect 100pf 100pf cpgnd dgnd agnd rf in a rf in b clk d at a le decoupling ca p aci t ors should be placed as close as possible t o the pins. c p 8 10 fref in 8.2nf 100nf 10f 100nf 10f 10pf 100nf 51? spi-com pa tible seria l bus 03685-028 figure 20 . local oscillator for a gsm base station transmitter
data sheet adf4153 rev. f | page 23 of 24 outline dimensions 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 21 . 16 - lead thin shrink small outline package [tssop] (ru - 16) dimensions shown in millimeters 3.75 bcs sq compliant to jedec standards mo-220-vggd-1 1 0.50 bsc pin 1 indic a t or 0.75 0.60 0.50 t o p view 12 max 0.80 max 0.65 ty p sea ting plane pin 1 indic a t or coplanarit y 0.08 1.00 0.85 0.80 0.30 0.23 0.18 0.05 max 0.02 nom 0.20 ref 2.25 2.10 sq 1.95 20 6 1 6 10 11 1 5 5 0.60 max 0.60 max 0.25 min for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 04-09-2012-b bot t om view exposed pad 4.10 4.00 sq 3.90 figure 22 . 20 - lead lead frame chip scale package [lfcsp_vq] 4 mm 4 mm body, very thin quad (cp - 20 - 1) dimensions shown in millimeter s
adf4153 data sheet rev. f | page 24 of 24 ordering guide model 1 , 2 temperature range package description package option adf4153bru ? 40c to +85c 16- lead thin shrink small outline package [tssop] ru -16 adf4153bru - reel7 ? 40c to +85c 16- lead thin shrink small outline package [tssop] ru -16 ad f4153bruz ? 40c to +85c 16- lead thin shrink small outline package [tssop] ru -16 adf4153bruz - rl ? 40c to +85c 16- lead thin shrink small outline package [tssop] ru -16 adf4153bruz - rl7 ? 40c to +85c 16- lead thin shrink small outline package [tssop] ru -16 adf4153yruz ? 40c to +125c 16- lead thin shrink small outline package [tssop] ru -16 adf4153yruz -rl ? 40c to +125c 16- lead thin shrink small outline package [tssop] ru -16 adf4153yruz - rl7 ? 40c to +125c 16- lead thin shrink small outline package [tssop] ru -16 adf4153bcpz ? 40c to +85c 20- lead lead frame chip scale package [lfcsp_vq] cp -20-1 adf4153bcpz -rl ? 40c to +85c 20- lead lead frame chip scale package [lfcsp_vq] cp -20-1 adf4153bcpz - rl7 ? 40c to +85c 20- lead lead frame chip scale package [lfcsp_ vq] cp -20-1 adf4153ycpz ? 40c to +125c 20- lead lead frame chip scale package [lfcsp_vq] cp -20-1 adf4153ycpz - rl ? 40c to +125c 20 - lead lead frame chip scale package [lfcsp_vq] cp - 20 - 1 adf4153ycpz - rl7 ? 40c to +125c 20- lead lead frame chip scale packag e [lfcsp_vq] cp -20-1 adf4153wyruz - r l 7 ? 40c to +125c 16- lead thin shrink small outline package [tssop] ru -16 ev - adf4153 sd1 z evaluation board 1 z = rohs compliant p art . 2 w = qualified for automotive applications . automotive products the adf4153wyruz - rl7 model is available with controlled manufacturing to support the qu ality and reliability requirements of automotive applications. note that th is automotive model may have specifications that differ from the commercial models; therefore, designers should review the specifications section of this data sheet carefully. only the automotive grade products shown are available for use in automotive applications. contact your local analog devices account representative for specific product ordering inform ation and to obtain the specific automotive reliability reports for th is mode l. i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). ? 2003 C 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d03685 - 0- 11/13(f)

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